
CY28548
......................Document #: 001-08400 Rev ** Page 18 of 30
each clock.
Figure 4 is an example showing the relationship of
clocks coming up.
PD#
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 3. Power down Assertion Timing Waveform
DOT 9 6 C
PD#
CP UC, 1 3 3 MHz
C P UT , 13 3MH z
S RCC 10 0MH z
U SB, 4 8 MH z
DOT 9 6 T
S RCT 1 0 0 MHz
Ts table
<1 .8 m s
PC I, 3 3 MH z
REF
Td r iv e _ PW R D N #
< 300
s , >2 00m V
Figure 4. Power down Deassertion Timing Waveform
FS _A , F S _B ,FS _C ,F S _D
CK_P W R G D
PW R G D _VR M
V D D C lock G en
C lock S tate
C lock O utputs
Clock VCO
0.2-0.3 m s
Delay
State 0
S tate 2
S tate 3
W ait for
VTT_P W R G D #
Sam ple Sels
Off
On
State 1
D evice is not affected,
V T T _P W RGD# is ignored
Figure 5. CK_PWRGD Timing Diagram